? 2001 fairchild semiconductor corporation ds012446 www.fairchildsemi.com january 1999 revised august 2001 74lvt162245 ? 74lvth162245 low voltage 16-bit transceiver with 3-state outputs and 25 ? series resistors in a port outputs 74lvt162245 74lvth162245 low voltage 16-bit transceiver with 3-state outputs and 25 ? series resistors in a port outputs general description the lvt162245 and lvth162245 contains sixteen non- inverting bidirectional buffers with 3-state outputs and is intended for bus oriented applications. the device is byte controlled. each byte has separate control inputs which can be shorted together for full 16-bit operation. the t/r inputs determine the direction of data flow through the device. the oe inputs disable both the a and b ports by placing them in a high impedance state. the lvt162245 and lvth162245 are designed with equivalent 25 ? series resistance in both the high and low states on the a port outputs. this design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. the lvth162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. these non-inverting transceivers are designed for low voltage (3.3v) v cc applications, but with the capability to provide a ttl interface to a 5v environment. the lvt162245 and lvth162245 are fabricated with an advanced bicmos technology to achieve high speed oper- ation similar to 5v abt while maintaining a low power dis- sipation. features input and output interface capability to systems at 5v v cc bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74lvth162245), also available without bushold feature (74lvt162245). live insertion/extraction permitted power up/down high impedance provides glitch-free bus loading a port outputs include equivalent series resistance of 25 ? making external termination resistors unnecessary and reducing overshoot and undershoot a port outputs source/sink 12 ma. b port outputs source/sink ? 32 ma/ + 64 ma functionally compatible with the 74 series 162245 latch-up performance exceeds 500 ma esd performance: human-body model > 2000v machine model > 200v charged-device model > 1000v also packaged in plastic fine pitch ball grid array (fbga) ordering code: note 1: bga package available in tape and reel only. order number package number package description 74lvt162245gx (note 1) bga54a (preliminary) 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide [tape and reel] 74lvt162245mea ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide [tube] 74LVT162245MEAX ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide [tape and reel] 74lvt162245mtd mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide [tube] 74lvt162245mtdx mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide [tape and reel] 74lvth162245gx (note 1) bga54a 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide [tape and reel] 74lvth162245mea ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide [tube] 74lvth162245mex ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide [tape and reel] 74lvth162245mtd mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide [tube] 74lvth162245mtx mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide [tape and reel]
www.fairchildsemi.com 2 74lvt162245 74lvth162245 logic symbol connection diagrams pin assignments for ssop and tssop pin assignment for fbga (top thru view) pin descriptions fbga pin assignments truth tables h = high voltage level l = low voltage level x = immaterial z = high impedance pin names description oe n output enable input (active low) t/r n transmit/receive input a 0 ?a 15 side a inputs/3-state outputs b 0 ?b 15 side b inputs/3-state outputs nc no connect 123456 a b 0 nc t/r 1 oe 1 nc a 0 b b 2 b 1 nc nc a 1 a 2 c b 4 b 3 v cc v cc a 3 a 4 d b 6 b 5 gnd gnd a 5 a 6 e b 8 b 7 gnd gnd a 7 a 8 f b 10 b 9 gnd gnd a 9 a 10 g b 12 b 11 v cc v cc a 11 a 12 h b 14 b 13 nc nc a 13 a 14 j b 15 nc t/r 2 oe 2 nc a 15 inputs outputs oe 1 t/r 1 llbus b 0 ?b 7 data to bus a 0 ?a 7 lhbus a 0 ?a 7 data to bus b 0 ?b 7 h x high-z state on a 0 ?a 7 , b 0 ?b 7 inputs outputs oe 2 t/r 2 llbus b 8 ?b 15 data to bus a 8 ?a 15 lhbus a 8 ?a 15 data to bus b 8 ?b 15 h x high-z state on a 8 ?a 15 , b 8 ?b 15
3 www.fairchildsemi.com 74lvt162245 74lvth162245 functional description the lvt162245 and lvth162245 contain sixteen non- inverting bidirectional buffers with 3-state outputs. the device is byte controlled with each byte functioning identi- cally, but independent of the other. the control pins can be shorted together to obtain full 16-bit operation. logic diagrams please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com 4 74lvt162245 74lvth162245 absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum rated conditions is not implied. note 3: i o absolute maximum rating must be observed. dc electrical characteristics symbol parameter value conditions units v cc supply voltage ? 0.5 to + 4.6 v v i dc input voltage ? 0.5 to + 7.0 v v o output voltage ? 0.5 to + 7.0 output in 3-state v ? 0.5 to + 7.0 output in high or low state (note 3) i ik dc input diode current ? 50 v i < gnd ma i ok dc output diode current ? 50 v o < gnd ma i o dc output current 64 v o > v cc output at high state ma 128 v o > v cc output at low state i cc dc supply current per supply pin 64 ma i gnd dc ground current per ground pin 128 ma t stg storage temperature ? 65 to + 150 c symbol parameter min max units v cc supply voltage 2.7 3.6 v v i input voltage 0 5.5 v i oh high-level output current b port ? 32 ma a port ? 12 i ol low-level output current b port 64 ma a port 12 t a free air operating temperature ? 40 + 85 c ? t/ ? v input edge rate, v in = 0.8v ? 2.0v, v cc = 3.0v 0 10 ns/v symbol parameter v cc t a = ? 40 c to + 85 c units conditions (v) min max v ik input clamp diode voltage 2.7 ? 1.2 v i i = ? 18 ma v ih input high voltage 2.7 ? 3.6 2.0 v v o 0.1v or v il input low voltage 2.7 ? 3.6 0.8 v v o v cc ? 0.1v v oh output high voltage a port 3.0 2.0 v i oh = ? 12 ma 2.7 ? 3.6 v cc ? 0.2 vi oh = ? 100 a b port 2.7 2.4 v i oh = ? 8 ma 3.0 2.0 i oh = ? 32 ma v ol output low voltage a port 3.0 0.8 v i ol = 12 ma 2.7 0.2 v i ol = 100 a b port 2.7 0.5 v i ol = 24 ma 3.0 0.4 i ol = 16 ma 3.0 0.5 i ol = 32 ma 3.0 0.55 i ol = 64 ma i i(hold) bushold input minimum drive 3.0 75 a v i = 0.8v (note 4) ? 75 v i = 2.0v i i(od) bushold input over-drive 3.0 500 a (note 5) (note 4) current to change state ? 500 (note 6) i i input current 3.6 10 a v i = 5.5v control pins 3.6 1v i = 0v or v cc data pins 3.6 ? 5v i = 0v 1v i = v cc i off power off leakage current 0 100 a0v v i or v o 5.5v
5 www.fairchildsemi.com 74lvt162245 74lvth162245 dc electrical characteristics (continued) note 4: applies to bushold versions only (74lvth162245). note 5: an external driver must source at least the specified current to switch from low-to-high. note 6: an external driver must sink at least the specified current to switch from high-to-low. note 7: this is the increase in supply current for each input that is at the specified voltage level rather than v cc or gnd. dynamic switching characteristics (note 8) note 8: characterized in ssop package. guaranteed parameter, but not tested. note 9: max number of outputs defined as (n). n ? 1 data inputs are driven 0v to 3v. output under test held low. symbol parameter v cc t a = ? 40 c to + 85 c units conditions (v) min max i pu/pd power up/down 0 ? 1.5v 100 a v o = 0.5v to 3.0v 3-state current v i = gnd to v cc i ozl 3-state output leakage current 3.6 ? 5 av o = 0.5v i ozl 3-state output leakage current 3.6 ? 5 av o = 0.0v (note 4) i ozh 3-state output leakage current 3.6 5 av o = 3.0v i ozh 3-state output leakage current 3.6 5 av o = 3.6v (note 4) i ozh + 3-state output leakage current 3.6 10 av cc < v o 5.5v i cch power supply current 3.6 0.19 ma outputs high i ccl power supply current 3.6 5 ma outputs low i ccz power supply current 3.6 0.19 ma outputs disabled i ccz + power supply current 3.6 0.19 ma v cc v o 5.5v, outputs disabled ? i cc increase in power supply current 3.6 0.2 ma one input at v cc ? 0.6v (note 7) other inputs at v cc or gnd symbol parameter v cc t a = 25 c units conditions (v) min typ max c l = 50 pf, r l = 500 ? v olp quiet output maximum dynamic v ol 3.3 0.8 v (note 9) v olv quiet output minimum dynamic v ol 3.3 ? 0.8 v (note 9)
www.fairchildsemi.com 6 74lvt162245 74lvth162245 ac electrical characteristics note 10: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). capacitance (note 11) note 11: capacitance is measured at frequency f = 1 mhz, per mil-std-883, method 3012. symbol parameter t a = ? 40 c to + 85 c units c l = 50 pf, r l = 500 ? v cc = 3.3v 0.3v v cc = 2.7v minmaxminmax t plh propagation delay data to a port output 1.0 4.0 1.0 4.6 ns t phl 1.0 3.7 1.0 4.1 t plh propagation delay data to b port output 1.0 3.5 1.0 3.9 ns t phl 1.0 3.5 1.0 3.9 t pzh output enable time for a port output 1.0 5.3 1.0 6.3 ns t pzl 1.0 5.6 1.0 7.2 t pzh output enable time for b port output 1.0 4.6 1.0 5.4 ns t pzl 1.0 5.3 1.0 6.9 t phz output disable time for a port output 1.5 5.6 1.5 6.3 ns t plz 1.5 5.5 1.5 5.5 t phz output disable time for b port output 1.5 5.4 1.5 6.1 ns t plz 1.5 5.1 1.5 5.4 t oshl a port output to output skew 1.0 1.0 ns t oslh (note 10) t oshl b port output to output skew 1.0 1.0 ns t oslh (note 10) symbol parameter conditions typical units c in input capacitance v cc = 0v, v i = 0v or v cc 4pf c i/o input/output capacitance v cc = 3.0v, v o = 0v or v cc 8pf
7 www.fairchildsemi.com 74lvt162245 74lvth162245 physical dimensions inches (millimeters) unless otherwise noted 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga54a
www.fairchildsemi.com 8 74lvt162245 74lvth162245 physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide package number ms48a
9 www.fairchildsemi.com 74lvt162245 74lvth162245 low voltage 16-bit transceiver with 3-state outputs and 25 ? series resistors in a port outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd48 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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